D Flip-Flop

A D flip-flop is a sequential element that follows the input pin d at the clock's given edge. D flip-flop is a fundamental component in digital logic circuits.

There are two types of D Flip-Flops being implemented: Rising-Edge D Flip Flop and Falling-Edge D Flip Flop.

D flip flop is an edge-triggered memory device that transfers a signal's value on its D input to its Q output when an active edge transition occurs on its clock input. Then, the output value is held until the next active clock cycle.

Flip flops are inferred using the edge triggered always statements. The always statement is edge-triggered by including either a posedge or negedge clause in the event list. Here are some examples of sequential always statements, such as:

always @(posedge Clock)
always @(negedge Clock)
always @(posedge Clock or posedge Reset)
always @(posedge Clock or negedge Reset)
always @(negedge Clock or posedge Reset)
always @(negedge Clock or negedge Reset)

If an asynchronously reset flip flop is being modeled, a second posedge or negedge clause is needed in the event list of the always statement. Also, most synthesis tools require that the reset must be used in if statement directly following the always statement, or after begin if it is in a sequential begin-end block.

Example

//Active low asynchronous reset
       always @(posedge Clock or negedge Reset)
       begin
            if (!Reset)
            …….
            ……..
end

Design 1: With the async active-low reset

module dff (input d,
              input rstn,
              input clk,
              output reg q);

	always @ (posedge clk or negedge rstn)
       if (!rstn)
          q <= 0;
       else
          q <= d;
endmodule

Hardware Schematic

Testbench

module tb_dff;
	reg clk;
	reg d;
	reg rstn;
	reg [2:0] delay;

    dff  dff0 ( .d(d),
                .rsnt (rstn),
                .clk (clk),
                .q (q));

    // Generate clock
    always #10 clk = ~clk;

    // Testcase
    initial begin
    	clk <= 0;
    	d <= 0;
    	rstn <= 0;

    	#15 d <= 1;
    	#10 rstn <= 1;
    	for (int i = 0; i < 5; i=i+1) begin
    		delay = $random;
    		#(delay) d <= i;
    	end
    end
endmodule

Design 2: With sync active-low reset

module dff (input d,
              input rstn,
              input clk,
              output reg q);

	always @ (posedge clk)
       if (!rstn)
          q <= 0;
       else
          q <= d;
endmodule

Hardware Schematic

Testbench

module tb_dff;
	reg clk;
	reg d;
	reg rstn;
	reg [2:0] delay;

    dff  dff0 ( .d(d),
                .rsnt (rstn),
                .clk (clk),
                .q (q));

    // Generate clock
    always #10 clk = ~clk;

    // Testcase
    initial begin
    	clk <= 0;
    	d <= 0;
    	rstn <= 0;

    	#15 d <= 1;
    	#10 rstn <= 1;
    	for (int i = 0; i < 5; i=i+1) begin
    		delay = $random;
    		#(delay) d <= i;
    	end
    end
endmodule

Next TopicT Flip Flop

← prev next →

For Videos Join Our Youtube Channel: Join Now

Feedback

Send your Feedback to [email protected]

Help Others, Please Share

Learn Latest Tutorials

Splunk

SPSS

Swagger

Transact-SQL

Tumblr

ReactJS

Regex

Reinforcement Learning

R Programming

RxJS

React Native

Python Design Patterns

Python Pillow

Python Turtle

Keras

Preparation

Aptitude

Reasoning

Verbal Ability

Interview Questions

Company Questions

Trending Technologies

Artificial Intelligence

AWS

Selenium

Cloud Computing

Hadoop

ReactJS

Data Science

Angular 7

Blockchain

Git

Machine Learning

DevOps

B.Tech / MCA

DBMS

Data Structures

DAA

Operating System

Computer Network

Compiler Design

Computer Organization

Discrete Mathematics

Ethical Hacking

Computer Graphics

Software Engineering

Web Technology

Cyber Security

Automata

C Programming

C++

Java

.Net

Python

Programs

Control System

Data Mining

Data Warehouse

Javatpoint Services

JavaTpoint offers too many high quality services. Mail us on [email protected], to get more information about given services.

Website Designing
Website Development
Java Development
PHP Development
WordPress
Graphic Designing
Logo
Digital Marketing
On Page and Off Page SEO
PPC
Content Development
Corporate Training
Classroom and Online Training
Data Entry

Training For College Campus

JavaTpoint offers college campus training on Core Java, Advance Java, .Net, Android, Hadoop, PHP, Web Technology and Python. Please mail your requirement at [email protected]
Duration: 1 week to 2 week

^{Like/Subscribe us for latest updates or newsletter}

Verilog Tutorial