Verilog Timeformat

Verilog timescale directive specifies time unit and precision for simulations.

Verilog $timeformat system function specifies %t format specifier reporting style in display statements such as $display and $strobe.

Syntax

• unit_number is the smallest time precision out of all `timescale directives used in the source code.
• precision represents the number of fractional digits for the current timescale.
• suffix_string is an option to display the scale alongside real time values.

Example 1: 1ns/1ps

Below is an example of how $timeformat affects the format of the time unit display.

Now executes the above code, and it will give the following output, such as:

xcelium> run
[T=10512] a=0
[T=10.51 ns] a=0
[T=10.51200ns] a=0
[T=10512.000 ns] a=0
[T=10512.00 ps] a=0
xmsim: *W,RNQUIE: Simulation is complete.

Example 2: 1ns/100ps

We consider the same example from above with a different timescale.

Above code produce the following output:

xcelium> run
[T=105] a=0
[T=10.50 ns] a=0
[T=10.50000ns] a=0
[T=10500.000 ns] a=0
[T=10500.00 ps] a=0
xmsim: *W,RNQUIE: Simulation is complete.

Example 3: 100ns/1ns

NOTE: #1 represents 100ns and hence #10 yields 1000ns.

And the output looks like:

xcelium> run
[T=1051] a=0
[T=1051.00 ns] a=0
[T=1051.00000ns] a=0
[T=1051000.000 ns] a=0
[T=1051000.00 ps] a=0
xmsim: *W,RNQUIE: Simulation is complete.